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 RFEL : Models - Polyphase DFT ( Ventrix Range )
 
   

This page describes a set of fixed-point models for the RFEL range of Polyphase DFT cores. Versions are available for Matlab and SystemView. Both versions use fixed point arithmetic throughout and have customisable bit-widths.

The models are designed to accurately represent the functionality of the RFEL Polyphase DFT cores. They have been tested against RFEL's standard Polyphase DFT implementation and are bit-true provided that the modelled bit-widths are correctly set to avoid overflow.

The models are designed to be fully parameterisable so as to encompass the widest possible range of requirements. Many of the modelled configurations are provided by RFEL as optimised off-the-shelf FPGA cores. Cores may also be tailor-made to meet higher specification requirements.


The Full Radix 2 Matlab Model Manual can be downloaded here

Features :

Parameter Matlab Model SystemView Model
DFT size Powers of 2 from 2 to 32M. The upper limit also depends on available memory.
Filter length Integers from 2 to 5x32M taps.The filter must be at least as long as the number of DFT points.
Oversampling
rate 		The models are not limited to critical sampling at the output. The output oversampling rate is specified in terms of the decimation through the model (see 'Decimation' below). The models are not limited to critical sampling at the output. The output oversampling rate can be any power of 2 from 1 to the DFT size.
Decimation Integers from 1 to the DFT size. Setting the decimation equal to the DFT size provides a critically sampled output; setting decimation to half the DFT size yields a twice oversampled output, and so on. n/a
Bin ordering Either unshifted: from [0, 1, 2, ..., K-1] or
shifted: [K/2, K/2+1, ..., K-2, K-1, 0, 1, 2, ..., K/2-1]
Input precision Customisable between 1 and 62 bits. See 'Data precision' below. Customisable between 1 and 52 bits. See 'Data precision' below.
Polyphase tap
precision 		Customisable between 1 and 62 bits. See 'Data precision' below. Customisable between 1 and 52 bits. See 'Data precision' below.
DFT precision Fully customisable at input and output and at all intermediate stages between 1 and 62 bits. See 'Data precision' below. Fully customisable at input and output and at all intermediate stages between 1 and 52 bits. See 'Data precision' below.
Twiddle
precision		 Customisable between 1 and 62 bits. See 'Data precision' below.
Processing type Block processing Sample processing
Block input size Equal to the decimation parameter set at initialisation n/a
Block output size Equal to the FFT Length n/a
Output Rate n/a Equal to the input rate multiplied by the Oversampling rate
Pipeline delay None
FFT Type
Radix-2 Decimation In Frequency.
Data precision Up to 62 bits of fixed point precision is supported throughout. Intermediate sums and products must not exceed 62 bits precision. Up to 52 bits of fixed point precision is supported at input and output.Intermediate sums and products must not exceed 62 bits precision.
Platforms Matlab for Windows. Tested on Windows 2000, Matlab version 6.5. SystemView for Windows. Tested on Windows 2000, SystemView 5.0.

Matlab Model

The Matlab Polyphase DFT model is implemented as a fully optimised MEX add-in and can therefore be called in the same way as any other function. Use of the Matlab model involves three stages: initialisation, processing and destruction.

Initialisation : The user specifies the model parameters (DFT size, Filter length and Decimation, Bin ordering shift switch, and all appropriate bit widths) and the function returns a handle. This handle is then used in all future processing.
Processing : The user streams data into the model and retrieves the output of the polyphase DFT.
Destruction : The user calls clear on the model, which then deallocates all associated memory.


SystemView Model

The SystemView Polyphase DFT model is implemented as a custom token and may be inserted into the processing chain in the same way as any other token.
The user specifies the model parameters (DFT size, Oversampling rate, Bin ordering switch, Filter length and all appropriate bit widths) via the given dialog box. Integer filter taps can be loaded from an ASCII file.

A floating-point SystemView model is also available. Higher Radix pipelined FFT cores are in development.