In many system designs using fixed point processing, the FPGA output bit width can become quite large and is often not in a format desirable for the following stages of the system. To overcome this issue RFEL provide integer to floating point conversion cores.
In this specific example RFEL provide a 64-bit Signed Integer to IEEE-754 32-bit Single Precision Floating Point Format Converter core. The core is provided in EDIF netlist form as a component.
The core converts 64-bit Signed Integer input values into 32-bit IEEE-754 Single Precision output values. The conversion process is pipelined so that a continuous series of values can be converted at the clock rate applied to the core. A 'nan' control input is provided to force the output of the core to a 'Not A Number' (NaN) value of all ones. This feature may be used to provide a unique 'sync' or 'idle' value that can be easily interpreted by down-steam processes
Features
:
| • |
Proven
in Xilinx and Altera devices |
| • |
Easy
migration to most FPGA Vendors devices and architectures. |
| • |
Other
data formats can be implemented |
| • |
Fully
synchronous design. |
Applications
| • |
FPGA
to DSP interfacing |
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