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The RF Engines
Window core is primarily intended for signal pre-conditioning in
high sample rate DSP systems. The Window can be provided with pre-loaded
or a programmable coefficients. The core processes continuous complex
data, with no gaps and is provided in EDIF netlist form as a component.
The fixed coefficient version architecture uses interpolation of
a limited logic-based look-up table, which results in hardware efficient
implementations, especially for large window lengths.
The programmable coefficient version architecture uses an area of
dual-port memory, provided with a user interface to program the
desired coefficient values. The coefficients are applied to weight
complex input data with the programmed characteristics.
The cores are designed to interface directly with the RFEL range
of Distributed Half Band Filters and Vectis HiSpeed FFT cores.
A datasheet for a specific version of the core is available for
download. Other variants can be supplied at low cost.
Basic
Window Structure :
Features
:
| • |
Proven
in Xilinx and Altera devices |
| • |
Easy
migration to most FPGA Vendors devices and architectures. |
| • |
Fixed
or programmable coefficients |
| • |
Provides
a high performance front-end for the RF Engines FFT architectures. |
| • |
Various
data input bit widths can be implemented |
| • |
Fully
synchronous design. |
Applications
| • |
FFT Windowing |
|
| • |
Signal
Conditioning |
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