RF Engines' fractional resampling cores for FPGA can be used to perform up-sampling or down-sampling of high-speed digital signals. The architectures are highly scalable, and support rate conversion of just one channel or thousands of channels simultaneously, whilst maintaining efficient use of silicon resources, and providing excellent filtering performance in order to mitigate the effects of aliasing.

Generic Fractional Resampler

RF Engines' Flexible Resampler architecture supports up-sampling or down-sampling of many channels simultaneously, and allows the rate change to be selected with resolution of less than one Hertz. When operating on multiple input channels, the architecture treats each channel independently, allowing different input/output sampling rates, and rate changes for each. Furthermore, the rate change required for each channel can be updated at runtime, without affecting the operation of other channels.

The Fixed Rate Converter architecture provides efficient fractional rate conversion for a single input channel with a sample rate up to 200MS/s. Each core performs either up-conversion or down-conversion at a fixed conversion rate.

The FPGA cores are provided as an EDIF netlist for either Xilinx or Altera FPGA devices, and are custom generated for each specific requirement to ensure a minimal FPGA footprint, and lowest power consumption. Like all RF Engines cores, the resamplers are supported by bit-true Matlab models, allowing early validation of the core through simulation, and thereby reducing risk.

The designs are licensed as Intellectual Property (IP) cores to equipment manufacturers and allow a low cost and reduced risk route to product.


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