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The HyperSpeed range is designed to be used in applications
where very high sample rates are required, achieving rates of up
to 6.4GS/s complex
The FFT pipeline is built from 'M' individual FFTs, each with a
transform length of 'N'-points. Common resources are shared between
the individual FFTs (such as twiddle factor generation, control
etc). Frequency-domain outputs from the N-point FFTs are 'twiddled'
and combined using an M-point DFT, which is implemented as a fully
parallel pipelined FFT.
The HyperSpeed architecture can support transform lengths
that are integer powers of two using existing 'off-the-shelf' building
blocks. Other transform lengths can be built using Matrix FFT prime-length
building blocks.
The FFT cores use fixed-point arithmetic, and have been developed
using a highly parallel mixed-radix architecture. Each core will
be factory configured to precise user specifications, ensuring maximum
silicon efficiency and performance for each application.
The designs will be supplied in a netlist form as a component ready
to be combined with the customer's own IP or as part of an integrated
design from RFEL.
Features
:
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Available
for Xilinx and Altera. |
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Continuous real time processing up to 6.4GS/s complex |
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1 to 32k points available in single chip solutions, |
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Optimised for the speed / silicon trade off. |
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Twiddle
bit and bit growth adjustable ( factory setting ). |
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Fully
Pipelined design. |
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Integer
powers of two, or prime length FFTs |
Applications
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Wide
band filter banks. |
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Communications
systems. |
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Electronic
warfare (radar, sonar, surveillance). |
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Medical
Instruments. |
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Spectrum
analysis. |
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Radio
Astronomy. |
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