The HyperLength FFT is designed to implement very long transforms with minimum memory bandwidth. Minimising memory bandwidth, maximises the processing bandwidth for a given FPGA + external RAM hardware configuration. The actual hardware configuration will dictate what transform lengths and continuous processing bandwidths are possible.

Based on a Xilinx Virtex II 3000 used in conjunction with SRAM memory a HyperLength design will support a 1M-point transform running at complex sample rates up to 200MS/s.The use of SDRAM, will allow transform lengths up to 256M-points, at rates up to 10MS/s.

The architecture uses a pair of pipeline FFTs (usually Vectis HiSpeed, QuadSpeed or Matrix FFTs) to implement an N-point and an M-point DFT, that together with data re-ordering and twiddle factor application form an (N x M)-point FFT. External RAM is used to perform three data re-ordering stages as shown.



Twiddle factors are generated arithmetically using logic within the FPGA rather than being stored in external memory

The FFT cores use fixed-point arithmetic, and have been developed using a mixed-radix architecture. Each core will be factory configured to precise user specifications, ensuring maximum silicon efficiency and performance for each application.

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