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ChannelCore64
can be used for extracting up to 64 narrowband channels from one
or two wideband ADC inputs. The core is based on a novel channelisation
architecture, which provides the flexibility traditionally associated
with DDC cores and ASIC devices, but with significantly greater
silicon efficiency.
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Features
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64 independent downconversion channels |
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Support for two 16-bit ADC inputs up to 220MS/s |
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Alias-free channel bandwidths, up to 687.5 kHz |
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Independent
tuning of channel centre frequencies with a resolution <0.01Hz |
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Fraction
resampler for setting output sample rates with a resolution <0.01Hz |
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Reconfigure
channels without affecting operation of other channels |
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End-to-end
dynamic range of >80dB |
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Gain
control |
ChannelCore64 is supplied as an EDIF netlist, and includes a VHDL model and test bench, and a bit-true Matlab model. The standard core is designed for use with Xilinx Virtex II Pro, Virtex-4 and Virtex-5 FPGA devices. Variants of the core can be provided for other FPGA families including Altera Stratix I / II / III.
Variants
of ChannelCore64 can be produced upon request to meet a specific
channelisation requirement. Please contact
us if you have a specific requirement that you would like to
discuss.
ChannelCore64
Functional Representation (click
to zoom)
Benefits
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Fits within a single Xilinx Virtex II Pro 30 |
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Replaces up to 16 four-channel DDC ASICs |
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At least 8-times more silicon efficient than standard DDC cores |
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Bit-true
Matlab models for system simulations |
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Custom
versions available optimised to application |
Applications
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Telecommunications
basestations |
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Satellite
ground stations |
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Software
defined radio |
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MIMO
receivers |
Awards
ChannelCore64
won the 'Embedded System Innovation of the Year' category in the 2006
'Elektra' European Electronic Awards.
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